1. Field of the Invention
The present invention relates to a method of forming a silicon-on-insulator structure, and more particularly, an ultra-uniform bond and etch back silicon-on-insulator semiconductor layer.
2. Discussion of the Related Art
Silicon-on-insulator (SOI) technology provides a promising method for fabrication of very large scale integration (VLSI) integrated circuits, in which the dimensions of transistors and other semiconductor structures are below one micrometer. SOI technology addresses a host of problems associated with VLSI, for example, providing greater isolation between devices. For CMOS applications, this isolation must prevent latch-up and at the same time, must not be provided at the expense of available chip space. Furthermore, the threshold voltage of CMOS devices critically depends on the thickness and uniformity of the SOI layer. New high performance CMOS device and circuit designs are based upon SOI material which is not only exceedingly thin, i.e., 100-200 nm thick, but also exceedingly uniform, i.e., within a few nanometers, across a silicon wafer of 4-8" in diameter.
One method of forming an SOI substrate includes bond and etch back silicon-on-insulator (BESOI) technology. A BESOI substrate is formed by oxidizing a handle wafer and/or a seed wafer, followed by bonding the two wafers. The active device region is generated on the seed wafer by lapping and etching to the desired silicon film thickness. BESOI technology thus provides a clean oxide/silicon interface with a minimal amount of defects and charge trapping states in the buried oxide. While this technology is suitable for the fabrication of 600 nm SOI, the presence of an etch stop is required to achieve SOI wafers with a nominal thickness of 500 nm or less.
Another method for producing a thin SOI semiconductor layer from a wafer structure comprising a silicon layer, an oxide isolation layer, and a handle wafer, is to etch trenches through the silicon layer down to the underlying oxide isolation layer. Polish stop pads (or etch stop pads) of a desired thickness are then formed or deposited within the trenches. The thickness of the polish stop pads corresponds to the desired resultant SOI semiconductor layer thickness. The silicon layer is then polished down, the polishing being stopped at the polish stop pads. The remaining silicon positioned between polish stop pads forms the SOI semiconductor layer of desired thickness upon which semiconductor device may subsequently be formed. Disadvantages of this method include the need for optimizing the pattern factor associated with the locations of the polish stop pads in the silicon layer. The pattern factor is critical. For example, spacing of polish stop pads too far from one another can cause dish-out or non-uniformity effects in the polished silicon. Such dish-out or non-uniformity is highly undesirable. On the other hand, having too large a pattern factor, i.e., too many polish stop pads, reduces the amount of available SOI semiconductor layer. In the latter instance, thin uniform SOI is obtainable, but not over the entire area of the wafer.
Another example of an etch stop for achieving SOI wafers with a nominal thickness of 500 nm or less has been providing a heavily doped boron region placed by diffusion or implantation into the silicon. Most of the silicon substrate underlying the boron doped etch stop region is removed by grinding and polishing and a remainder portion thereof is selectively etched using an etchant consisting of ethylene diamine and pyrocatechol. With this etchant, nominal selectivity ratios of 1000:1 are reported for etch rates of undoped silicon compared to the etch rate of the very heavily doped boron etch stop region. A disadvantage of using a heavily doped boron region however is that boron is a p-type dopant in silicon. Additionally, both implantation and diffusion of boron results in residual p-type doping of the silicon film. Still further, boron incorporated by ion implantation and annealing results in the generation of threading dislocations in the device region. Performance of devices made from these SOI materials is undesirably compromised thereby. Most of all, the etch stop layer or region created by diffusion or implantation is by its creation, broad and diffuse, and, when used as described above, results in an SOI layer which is neither thin nor uniform across the entire silicon wafer.
Another method of forming a thin SOI semiconductor layer involving the use of an etch stop layer is disclosed in U.S. Pat. No. 5,013,681 issued to Godbey et al. on May 7, 1991. The method of the '681 patent includes forming a strained silicon germanium (SiGe) etch-stop layer upon a silicon substrate, forming a silicon cap layer upon the strained etch-stop layer, and bonding the silicon cap layer to a mechanical substrate. The silicon substrate and the strained etch stop layer are then removed without removing underlaying portions of the silicon cap layer, whereby the underlaying portions of the silicon cap layer remain on the mechanical substrate to form the thin SOI layer. A disadvantage of using the strained SiGe etch stop layer is that the selectivity of strain sensitive etchants is small and ultra-uniform SOI is thereby not obtainable.
Additionally, the '681 patent teaches a method of using a strained SiGe etch stop layer on top of an ion implanted boron etch stop layer to cap and prevent boron diffusion into the SOI layer, thus enabling higher selectivity etchants, available for boron etch stop layers, to be used. Because of the ion implanted nature of the boron etch stop layer, the etch stop is broad and diffuse, and thus the resulting SOI layer is not exceedingly uniform. Furthermore, the ion implanted layer has dislocations and defects which ultimately get transferred into the SOI layer.
The major inadequacy of the methods of the '681 patent and earlier methods in attaining ultra thin and extremely uniform SOI arises from the fact that commercially available silicon wafers used as the starting substrates are not of exactly uniform thickness across their diameters, typically varying by 10 to 20 microns across a five inch diameter wafer with a nominal thickness of 600 microns. This initial thickness variation is disadvantageously transferred into the silicon cap layer. For example, with an etch rate selectivity ratio of 1:1000 and an initial thickness variation in a bonded silicon wafer pair of 20 microns, the final SOI thickness variation may be theoretically expected to be no better than 20 nm (i.e., 20 .mu.m/1000=20 nm). For ultra-thin SOI thicknesses of 0.1 .mu.m or less, this final thickness variation of 20 nm is unacceptable.
While use of such highly selective etchants seems desirable in actual practice, there are drawbacks associated with them. The highly selective etchants are invariably anisotropic and often produce faceted or rough surfaces. Rough surfaces are highly undesirably for CMOS applications. Furthermore, highly selective etchants, such as ethylene diamine and pryocatechol have been judged to be unduly hazardous. Ethylene diamine is reported to cause allergic respiratory sensitization and pyrazine is described as a toxic corrosive. The use of these etchants in a high volume manufacturing process creates undue risk during their use and subsequent disposal thereof.
It is therefore desirable to provide a method of producing an SOI layer using etchants such as potassium hydroxide (KOH) or ammonium hydroxide (NH.sub.4 OH) which have lower etch selectivities in the range of 500:1 to 100:1 and which do not pose significant health and environmental hazards.
It is further desirable to provide a method for forming an SOI semiconductor layer which is highly uniform and suitable for ultra-thin SOI structures. Such a method should provide for good thickness control for producing an SOI semiconductor layer having a thickness variation of a few nanometers. Such a method should also be suitable for use in large scale manufacturing of SOI wafers using commercially available silicon substrates and environmentally compatible etch chemistries.